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Translating network models to parallel hardware in NEURON (Hines and Carnevale 2008)
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Shows how to move a working network model written in NEURON from a serial processor to a parallel machine in such a way that the final result will produce numerically identical results on either serial or parallel hardware.
Hines ML, Carnevale NT (2008) Translating network models to parallel hardware in NEURON.
J Neurosci Methods
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Carnevale, Ted [Ted.Carnevale at Yale.edu];
Hines, Michael [Michael.Hines at Yale.edu];
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