Translating network models to parallel hardware in NEURON (Hines and Carnevale 2008)

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Accession:96444
Shows how to move a working network model written in NEURON from a serial processor to a parallel machine in such a way that the final result will produce numerically identical results on either serial or parallel hardware.
Reference:
1 . Hines ML, Carnevale NT (2008) Translating network models to parallel hardware in NEURON. J Neurosci Methods 169:425-55 [PubMed]
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Model Information (Click on a link to find other models with that property)
Model Type: Realistic Network;
Brain Region(s)/Organism:
Cell Type(s):
Channel(s):
Gap Junctions:
Receptor(s):
Gene(s):
Transmitter(s):
Simulation Environment: NEURON;
Model Concept(s): Simplified Models; Methods;
Implementer(s): Carnevale, Ted [Ted.Carnevale at Yale.edu]; Hines, Michael [Michael.Hines at Yale.edu];
: based on ExpSyn
: PARAMETERs sid and cid are used to manage and decipher network architecture

NEURON {
:	POINT_PROCESS ExpSyn
	POINT_PROCESS ExpSid
	RANGE tau, e, i, sid, cid
	NONSPECIFIC_CURRENT i
}

UNITS {
	(nA) = (nanoamp)
	(mV) = (millivolt)
	(uS) = (microsiemens)
}

PARAMETER {
	tau = 0.1 (ms) <1e-9,1e9>
	e = 0	(mV)
	: following are used to help decipher and manage network architecture 
	sid = -1 (1) : synapse id, from cell template
	cid = -1 (1) : id of cell to which this synapse is attached
	             : in parallel context this value should be assigned the cell's gid
}

ASSIGNED {
	v (mV)
	i (nA)
}

STATE {
	g (uS)
}

INITIAL {
	g=0
}

BREAKPOINT {
	SOLVE state METHOD cnexp
	i = g*(v - e)
}

DERIVATIVE state {
	g' = -g/tau
}

NET_RECEIVE(weight (uS)) {
	state_discontinuity(g, g + weight)
}