Inhibition of bAPs and Ca2+ spikes in a multi-compartment pyramidal neuron model (Wilmes et al 2016)

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Accession:187603
"Synaptic plasticity is thought to induce memory traces in the brain that are the foundation of learning. To ensure the stability of these traces in the presence of further learning, however, a regulation of plasticity appears beneficial. Here, we take up the recent suggestion that dendritic inhibition can switch plasticity of excitatory synapses on and off by gating backpropagating action potentials (bAPs) and calcium spikes, i.e., by gating the coincidence signals required for Hebbian forms of plasticity. We analyze temporal and spatial constraints of such a gating and investigate whether it is possible to suppress bAPs without a simultaneous annihilation of the forward-directed information flow via excitatory postsynaptic potentials (EPSPs). In a computational analysis of conductance-based multi-compartmental models, we demonstrate that a robust control of bAPs and calcium spikes is possible in an all-or-none manner, enabling a binary switch of coincidence signals and plasticity. ..."
Reference:
1 . Wilmes KA, Sprekeler H, Schreiber S (2016) Inhibition as a Binary Switch for Excitatory Plasticity in Pyramidal Neurons. PLoS Comput Biol 12:e1004768 [PubMed]
Model Information (Click on a link to find other models with that property)
Model Type: Neuron or other electrically excitable cell;
Brain Region(s)/Organism: Neocortex; Hippocampus;
Cell Type(s): Hippocampus CA1 pyramidal cell; Neocortex V1 L6 pyramidal corticothalamic GLU cell;
Channel(s):
Gap Junctions:
Receptor(s):
Gene(s):
Transmitter(s):
Simulation Environment: NEURON; Python;
Model Concept(s): Dendritic Action Potentials; Synaptic Plasticity; Synaptic Integration;
Implementer(s): Wilmes, Katharina A. [katharina.wilmes at googlemail.com];
Search NeuronDB for information about:  Hippocampus CA1 pyramidal cell; Neocortex V1 L6 pyramidal corticothalamic GLU cell;
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WilmesEtAl2016
mod_files
cad2.mod *
hh2.mod *
hh3.mod
it2.mod *
kap.mod *
kca.mod *
kdrca1.mod *
na3.mod *
na3dend.mod
na3shifted.mod *
sca.mod *
stdp_ca.mod
stdp_m.mod
                            
: STDP by Hines, modified by Michiel to implement additive STDP as in Song et al 2000

NEURON {
        POINT_PROCESS ExpSynSTDP
        RANGE tau, e, i, dd, dp, dtau, ptau, thresh, wmax, wmin, D
        NONSPECIFIC_CURRENT i
}

UNITS {
        (nA) = (nanoamp)
        (mV) = (millivolt)
        (uS) = (microsiemens)
}

PARAMETER {
        tau     = 3 (ms) <1e-9,1e9>
        e       = 0     (mV)
        dd      = 0.001 <0,1>   : depression factor (relative!)
        dp      = 0.00106       : potentiation factor (relative!)
        dtau    = 20 (ms)   : depression effectiveness time constant
        ptau    = 20 (ms)   : Bi & Poo (1998, 2001)
        thresh  = -20 (mV)      : postsynaptic voltage threshold
        wmax    = 0.001 (uS)
        wmin    = 0 (uS)
}

ASSIGNED {
        v (mV)
        i (nA)
    D
        tpost (ms)
}

STATE {
        g (uS)
}

INITIAL {
        g = 0
        D = 0
        tpost = -1e9
        net_send(0, 1)
}

BREAKPOINT {
        SOLVE state METHOD cnexp
        i = g*(v - e)
}

DERIVATIVE state {
        g' = -g/tau
}

NET_RECEIVE(w (uS), P, tpre (ms), wsyn) {
        INITIAL { P = 0 tpre = -1e9 wsyn = w}
        if (flag == 0) { : presynaptic spike  (after last post so depress)      
        :printf("entrym flag=%g t=%g w=%g A=%g tpre=%g tpost=%g g=%g\n", flag, t, w, P, tpre, tpost,g)
        printf("wsyn=%g dp = %g wmax = %g\n", wsyn,dp,wmax)
        
        g = g + wsyn
        P = P*exp((tpre-t)/ptau) + dp
        tpre = t
        wsyn = wsyn + wmax * D * exp((tpost-t)/dtau) : interval is negative
        if (wsyn < wmin) { wsyn = wmin }
        }else if (flag == 2) { : postsynaptic spike                             
        :printf("entry flag=%g t=%g tpost=%g\n", flag, t, tpost)
        FOR_NETCONS(w1, P1, tpre1, wsyn1) {
            :D1 = D1*exp((tpost-t)/dtau) - dd
            wsyn1 = wsyn1 + wmax * P1 * exp(-(t - tpre1)/ptau) : interval is positive
            if (wsyn1 > wmax) { wsyn1 = wmax }
        }
        D = D*exp((tpost-t)/dtau) - dd
        :wsyn =  0
        :wsyn = wsyn + wmax * P * exp(-(t - tpre)/ptau)
        :if (wsyn > wmax) { wsyn = wmax }
        tpost = t
        } else { : flag == 1 from INITIAL block                                 
        :printf("entry flag=%g t=%g\n", flag, t)
                WATCH (v > thresh) 2
        }
}

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